1. Field of the Invention
The present invention relates to a board for mounting a semiconductor chip thereon, a method of fabricating such a board, a semiconductor device, and a method of fabricating such a semiconductor device, and more particularly to a semiconductor device in a BGA (Ball Grid Array) type package, a multilayer wiring board for use in such a semiconductor device, and methods of fabricating such a semiconductor device and such a multilayer wiring board.
2. Description of the Related Art
Heretofore, boards for mounting semiconductor chips thereon to make up BGA-type semiconductor devices comprise a glass epoxy multilayer wiring board or a build-up multilayer wiring board which is produced by stacking conductive layers and insulating layers repeatedly on a support plate of metal and then removing the support plate.
The glass epoxy multilayer wiring board is made of an organic material having low heat resistance as a base material. Therefore, the glass epoxy multilayer wiring board is disadvantageous in that when heated, it is warped or distorted, presenting an obstacle to efforts to form fine interconnections in the fabrication of wiring boards and possibly reducing the reliability of connections over a long period of time after components have been mounted on the board. The build-up multilayer wiring board, which is designed to eliminate the above shortcomings, has a multilayer circuit constructed on one surface of a flat metal sheet according to a build-up process for eliminating possible causes of heat-induced warpages and distortions, thereby making it possible to produce fine interconnections in the fabrication process and to improve the reliability of connections over a long period of time.
A process of forming a BGA pad (electrode pad) on a metal sheet, thereafter producing a multilayer circuit according to a build-up process, and then removing the metal sheet is disclosed in Japanese laid-open patent publications Nos. 2001-36238, 2001-44578, 2001-44583, and 2001-44589. According to a BGA package fabrication process (see FIGS. 1A and 1B of the accompanying drawings) disclosed in the above publications, after BGA pads 31 are formed on a metal sheet (not shown), conductive layer 32 is formed on BGA pads 31, and then insulating layer 33 is formed on conductive layer 32 and metal sheet, after which via 34 is formed through insulating layer 33. Although not shown, a semiconductor chip such as an LSI chip or the like is mounted on via 34, after which the metal sheet is removed. Conductive layer 32 includes connection terminals 32a positioned directly above BGA pads 31 and having an area greater than BGA pads 31, and interconnections 32b extending from connection terminals 32a to via 34.
With the structure shown in FIGS. 1A and 1B, since conductive layer 32 is formed directly over BGA pads 31, interconnections 32b connected through via 32 to the semiconductor chip are located in limited positions so as not to be short-circuited to other BGA pads 31. Thus, the interconnections cannot be formed over many other BGA pads 31, and should be formed in those areas which are free of other BGA pads 31. The interconnections are also required to be kept out of contact with other connection terminals 32a. As a result, interconnections 32b individually connecting from a plurality of BGA pads 31 forming columns to the semiconductor chip cannot be packed in a high density. Specific examples of formed patterns of interconnections 32b which represent the numbers of columns of BGA pads 31 and corresponding interconnections 32b are shown in Table 1 below. BGA pads 31 have a diameter of 250 μm and are spaced by a pitch of 0.5 mm, and via 34 has a diameter of 75 μm.
TABLE 1Max. number of inter-Width and spacingNumber of columnsconnections be-of inter-of BGA padstween padsconnections2150 μm4327 μm6519 μm9812 μm
As shown in Table 1, as the number of columns of BGA pads 31 increases, the width and spacing of interconnections 32b decrease. Since the fabrication process suffers limitations that make it impossible to form interconnections 32 whose width and spacing are 20 μm or less, the number of actually available columns of BGA pads 31 is limited to five or less.
Multilayer interconnection boards for BGA packages are required to meet two requirements about the productivity of a solder ball mounting process and the bonding strength of solder balls. These two requirements will be described in detail below.
The productivity of a solder ball mounting process refers to the accuracy of a process of placing solder balls 35 (see FIGS. 2A through 2C of the accompanying drawings) on BGA pad 31. In this process, solder balls 35 are placed on BGA pad 31 coated with a flux or a solder paste and arrayed, after which solder balls 35 are joined to BGA pad 31 by reflow heating. When solder balls 35 are subjected to reflow heating, solder balls 35 may possibly move due to different flux quantities and different flux activity levels on BGA pad 31, resulting in soldering failures such that adjacent solder balls 35 may join each other and fall off BGA pad 31.
The bonding strength of solder balls refers to the reliability of connections over a long period of time after the semiconductor device in the BGA package is mounted on another board. The bonding between BGA pad 31 and solder balls 35 may possibly become unreliable owing to the difference between the coefficient of thermal expansion of the semiconductor device and the coefficient of thermal expansion of the board on which the semiconductor device is mounted. Particularly, BGA package semiconductor devices of more pins and greater outer profiles tend to have smaller solder bonding strength and suffer more solder joint cracking.
Generally, as shown in FIGS. 2A through 2C, the surface of BGA pad 31 on the multilayer wiring board may be positioned in three different ways with respect to the surface of insulating layer 33. These three different ways shown in FIGS. 2A through 2C provide respective different properties shown in Table 2.
TABLE 2Position of sur-Productivity offace of BGA padsolder ball mount-Bonding strength(FIGS.)ing processof solder ballsLower than insu-◯Xlating layer sur-face (FIG. 2A)Lying flush withXXinsulating layersurface (FIG. 2B)Higher than insu-X◯lating layer sur-face (FIG. 2C)
As shown in FIG. 2A, if the surface of BGA pad 31 is lower than the surface of insulating layer 33, then since solder ball 35 is held in position in a reflow process, the productivity of the solder ball mounting process is high and the yield is increased. However, solder ball 35 is joined to only the principal surface of BGA pad 31, the area of contact between BGA pad 31 and solder ball 35, i.e., the joining area therebetween, is small, and hence the bonding strength of solder ball 35 is small, tending to cause cracking in the joint. As shown in FIG. 2C, if the surface of BGA pad 31 is higher than the surface of insulating layer 33, then because solder ball 35 is joined to not only the principal surface of BGA pad 31, but also side surfaces thereof, the joining area between BGA pad 31 and solder ball 35 is large, and the bonding strength of solder ball 35 is large, making it difficult to cause cracking in the joint. However, since solder ball 35 is not held stably in position but is liable to move in the reflow process, the productivity of the solder ball mounting process is low. As shown in FIG. 2B, if the surface of BGA pad 31 lies flush with the surface of insulating layer 33, then the productivity of the solder ball mounting process is low and the bonding strength of solder ball 35 is small. With either one of the bonding patterns shown in FIGS. 2A through 2C, it is impossible to simultaneously meet the requirements about both the productivity of the solder ball mounting process and the bonding strength of solder ball 35.
According to the process of fabricating multilayer wiring boards, BGA pad 31 is formed on flat insulating layer 3. Therefore, solder resist 36 (see FIGS. 3A through 3B of the accompanying drawings) may be formed on insulating layer 33 to provide a desired surface configuration around BGA pad 31.
FIG. 3A shows a so-called over-resist structure in which the surface of solder resist 36 is higher than the surface of BGA pad 31. In the over-resist structure, BGA pad 31 has its outer periphery covered with solder resist 36. Until solder ball 35 is fixed after it is mounted in position in the reflow process, solder ball 35 is not displaced, and BGA pad 31 and insulating layer 33 lying therebeneath are held in intimate contact with each other. The productivity of the solder ball mounting process is good, but the bonding strength of solder ball 35 is poor. FIG. 3B shows a so-called non-over-resist structure (normal resist structure) in which solder resist 36 does not cover the surface of BGA pad 31. In the non-over-resist structure, the solder flows around the side surfaces of BGA pad 31 to join solder ball 35 as mentioned above. Though the bonding strength of solder ball 35 is high, the BGA pad 31 and insulating layer 33 are not held in intimate contact with each other, with the result that the productivity of the solder ball mounting process is poor.
Japanese laid-open patent publication No. 2001-230513 discloses a partial combination of the over-resist and non-over-resist structures in which solder resist 36 has an elliptical opening defined therein.
Japanese laid-open patent publication No. 2001-230339 reveals an over-resist structure in which a criss-cross recess is defined in BGA pad 31 for increasing the bonding strength according to the soldering process.
Japanese laid-open patent publication No. 11-54896 shows an over-resist structure in which only a portion of solder resist 36 which extends around BGA pad 31 is removed to the height of the surface of BGA pad 31 or lower by laser ablation, so that BGA pad 31 has a lower portion surrounded by solder resist 36 and an upper portion bonded to solder ball 35.
All the above disclosed structures are based on the arrangement that solder resist 36 is formed on insulating layer 33. The laminated assembly of such different materials suffers a strain caused by stresses. Specifically, since strains concentrate on the corners of the interface between layers 33, 36, the assembly tends to cause fractures such as cracking due to shocks imposed when the assembly falls by gravity and hits a hard object or thermal shocks. Even if solder resist 36 and insulating layer 33 lying therebeneath are of one organic material, they are liable to be broken apart because the organic material develop different mechanical properties depending on the thermal hysteresis. It is preferable that solder resist 36 and insulating layer 33 be not separate from each other, but formed of the same material according to the same process.